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10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer ADV7400A
FEATURES
Three 10-bit ADCs sampling up to 110 MHz 12 analog input channel mux NTSC/PAL/SECAM color standards support Adaptive digital line length tracking (ADLLTTM), signal processing, and enhanced FIFO management give mini TBC functionality 525p/625p component progressive scan support 720p/1080i component HDTV support Digitizes RGB graphics up to 1280 x 1024 @ 60 Hz (SXGA) 24-bit digital input port supports data from DVI/HDMI Rx IC Any-to-any 3 x 3 color-space conversion matrix Industrial temperature range (-40C to +85C) 12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface Programmable interrupt request output pin
GENERAL DESCRIPTION
The ADV7400A is a high quality, single chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R BT.656 format. The ADV7400A also supports decoding a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other HD and SMPTE standards. Graphic digitization is also supported by the ADV7400A; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. The ADV7400A contains two main processing sections. The first is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. For more specific descriptions of the ADV7400A features, see the Detailed Functionality and Detailed Description sections.
APPLICATIONS
LCD/DLPTM rear projection HDTVs PDP HDTVs CRT HDTVs LCD/DLP front projectors LCD TV (HDTV-ready) HDTV STBs with PVR Hard disk-based video recorders Multiformat scan converters DVD recorders with progressive scan input support
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE DATA PREPROCESSOR 10 RGB YPrPb YC AND CVBS SOG SOY HS_IN/ CS_IN VS_IN SCLK1 SDA1 SCLK2 SDA2 ALSB DCLK_IN DE_IN HS_IN/ CS_IN VS_IN 12-CH INPUT MATRIX CLAMP CLAMP CLAMP A/D 10 A/D 10 A/D HS/CS & VS SYNC PROCESSING & CLOCK GENERATION CONTROL
MUX
(A) (B) SYNC COLOR SPACE (C) CONVERTER (A) (B) DECIMATION (C) AND DOWNSAMPLING FILTERS
DIGITAL PROCESSING BLOCK COMPONENT PROCESSOR SYNC SOURCE STANDARD & POLARITY IDENTIFICATION DETECT SYNC EXTRACTION AV CODE INSERTION MACROVISION(R) TIMING CONTROL & CGMS DETECTION DIGITAL FINE CLAMP GAIN & OFFSET CONTROL
OUTPUT FORMATTER
8
8
PIXEL DATA
8
CONTROL
NOISE & CALIBRATION MEASUREMENT STANDARD DEFINITION PROCESSOR
LUMA FILTERING DUAL PORT SERIAL INTERFACE CONTROL (1) & VBI DATA (2) CONTROL & DATA CONTROL SERIAL INTERFACE 24 DIGITAL VIDEO INPUT PORT SYNC/CONTROL 10 CVBS 24 DVI/HDMI DIGITAL INTERFACE CHROMA FILTERING & DEMODULATION DIGITAL CLAMP & GAIN CONTROL DIGITAL CLAMP & GAIN CONTROL ADAPTIVE SYNC EXTRACTION (ADLLT)
LUMA RESAMPLER 2D 4H COMB FILTER RESAMPLE CONTROL AV CODE INSERTION
HS VS FIELD/DE LLC1 SFL/ SYNC_OUT INT
CHROMA RESAMPLER CTI 2D 4H COMB FILTER
GLOBAL CONTROL & VBI DATA SLICER MACROVISION DETECTION
Figure 1. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05000-001
ADV7400A TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Video Specifications ......................................................................... 4 Timing Characteristics..................................................................... 5 Analog Specifications....................................................................... 6 Thermal Specifications ................................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Detailed Functionality ................................................................... 10 Analog Front End ....................................................................... 10 SDP Pixel Data Output Modes ................................................. 10 CP Pixel Data Output Modes.................................................... 10 Composite and S-Video Processing......................................... 10 Component Video Processing .................................................. 10 RGB Graphics Processing ......................................................... 11 Digital Video Input Port ............................................................ 11 General Features......................................................................... 11 Detailed Description ...................................................................... 12 Analog Front End....................................................................... 12 Standard Definition Processor (SDP)...................................... 12 Component Processor (CP)...................................................... 12 Timing Diagrams............................................................................ 14 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
3/05--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Updated Outline Dimensions ....................................................... 16 10/04--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADV7400A ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, nominal input range = 1.6 V, operating temperature range, unless otherwise noted. Table 1. Electrical Characteristics1,2
Parameter STATIC PERFORMANCE3 Resolution (each ADC) Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Differential Nonlinearity Differential Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage XTAL High Voltage XTAL Low Voltage Input High Voltage Input Low Voltage Input Current Input Capacitance6 DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance6 POWER REQUIREMENTS6 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current Power-Down Current Green Mode Power-Down Power-Up Time
1 2
Symbol N INL INL INL INL DNL DNL DNL DNL VIH VIL VIH VIL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD IPWRDN IPWRDNG TPWRUP
Test Conditions
Min
Typ
Max 10 2.5
Unit Bits LSB LSB LSB LSB LSB LSB LSB LSB V V V V V V A A pF V V A A pF V V V V mA mA mA mA mA mA mA mA mA mA ms
BSL at 27 MHz (at a 10-bit level) BSL at 54 MHz (at a 10-bit level) BSL at 74 MHz (at a 10-bit level) BSL at 110 MHz (at an 8-bit level)4 At 27 MHz (at a 10-bit level) At 54 MHz (at a 10-bit level) At 74 MHz (at a 10-bit level) At 110 MHz (at an 8-bit level)4 2
0.6 -0.6/+0.7 -1.2/+1.5 -0.9/+1.6 -0.2/+0.25 -0.2/+0.25 0.8 -0.2/+1.5
-0.3/+0.7
0.8 Pin 38 Pin 38 HS_IN, VS_IN low trigger mode HS_IN, VS_IN low trigger mode Pins listed in Note 5 All other input pins 1.2 0.4 0.7 -60 -10 0.4 +60 +10 10
ISOURCE = 0.4 mA ISINK = 3.2 mA Pins listed in Note 7 All other output pins
2.4 0.4 60 10 20 1.65 3.0 1.65 3.15 1.8 3.3 1.8 3.3 82 62 2 17 10.5 6 85 218 1.5 12.5 20 2 3.6 2 3.45
CVBS input sampling at 54 MHz Graphics RGB sampling at 110 MHz4 CVBS input sampling at 54 MHz Graphics RGB sampling at 110 MHz4 54 MHz 110 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 110 MHz4 Sync bypass function
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C. 3 All ADC linearity tests performed at input range of full scale are -12.5%, and at zero scale they are +12.5%. 4 Specifications for the ADV7400AKSTZ-110 and the ADV7400ABSTZ-110 only. 5 Pins: 1, 2, 3, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100. 6 Guaranteed by characterization. 7 Pins: 45, 34, 33, 32, 31, 30, 29, 24, 14, 13 (P20 to P29). Rev. A | Page 3 of 16
ADV7400A VIDEO SPECIFICATIONS
AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise noted. Table 2. Video Specifications1, 2, 3
Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock in Time Sync Depth Range Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy
1 2
Symbol DP DG LNL
Test Conditions CVBS I/P, modulated 5 step CVBS I/P, modulated 5 step CVBS I/P, 5 step Luma ramp Luma flat field
Min
Typ 0.5 0.5 0.5
Max 0.7 0.7 0.7
Unit degree % % dB dB dB
54 58
56 60 60 +5 70 1.3 60
-5 40
20 5 2 100 HUE CL_AC 5 0.5 0.4 0.2 CVBS, 1 V input CVBS, 1 V input 1 1 1 1
200 200
% Hz kHz line % % field line degree % % % degree % % %
400
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C. 3 Guaranteed by characterization.
Rev. A | Page 4 of 16
ADV7400A TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise noted. Table 3. Timing Characteristics1, 2, 3
Parameter SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC1 Frequency Range4 I2C(R) PORT SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA and CONTROL OUTPUTS Data Output Transition Time (SDP) Data Output Transition Time (SDP) Data Output Transition Time (CP) Data Output Transition Time (CP) Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 DATA and CONTROL INPUTS Input Setup Time Input Hold Time
1 2
Symbol Test Conditions
Min
Typ 27.0
Max
Unit MHz ppm kHz MHz kHz s s s s ns ns ns s ms
14.8 12.825
50 110 110 400
t1 t2 t3 t4 t5 t6 t7 t8
0.6 1.3 0.6 0.6 100 300 300 0.6 5
t9:t10
45:55
55:45 % duty cycle 3.4 2.4 1.1 2.2 ns ns ns ns ns ns ns ns ns ns ns ns
t11 t12 t13 t14 t15 t16 t17 t18 t19 t20
Negative clock edge to start of valid data End of valid data to negative clock edge End of valid data to negative clock edge Negative clock edge to start of valid edge Positive clock edge to end of valid data Start of valid data to positive clock edge Negative clock edge to end of valid data Start of valid data to negative clock edge HS_IN, VS_IN DE_IN, data inputs HS_IN, VS_IN DE_IN, data inputs
-2.7 + TLLC1/4 -1.3 + TLLC1/4 -2.1 + TLLC1/4 -0.9 + TLLC1/4 9 2.2 7 1
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C. 3 Guaranteed by characterization. 4 Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80. 5 DDR timing specifications depend on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. A | Page 5 of 16
ADV7400A ANALOG SPECIFICATIONS
AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise noted. Table 4. Analog Specifications1, 2, 3
Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Voltage Clamp Level Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current
1 2 3
Symbol
Test Conditions
Min
Typ 0.1 10 1.7 0.75 0.75 60 60
Max
Unit F M V mA mA A A
Clamps switched off SDP only SDP only SDP only SDP only
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C. Guaranteed by characterization.
THERMAL SPECIFICATIONS
Table 5. Thermal Specifications
Thermal Characteristic Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance Symbol JC JA Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane (still air) Typ 7 30 Unit C/W C/W
Rev. A | Page 6 of 16
ADV7400A ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO - PVDD DVDDIO - DVDD AVDD - PVDD AVDD - DVDD Analog Inputs to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V -0.3 V to +0.3V -0.3 V to +0.3 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V AGND - 0.3 V to AVDD + 0.3 V 150C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 7 of 16
ADV7400A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HS_IN/CS_IN FIELD/DE SCLK1 DGND DE_IN VS_IN ALSB RESET
78
DVDD
SDA1
100
99
95
89
88
87
84
77
SOY
93
92
82
97
96
91
90
86
85
81
80
98
94
P32 P31 INT HS/CS DGND DVDDIO P15 P14 P13 P12 DGND DVDD P29 P28 SFL/SYNC_OUT SCLK2 DGND DVDDIO SDA2 P11 P10 P9 P8 P27 P7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN 1
83
79
76
AIN6
75 74 73 72 71 70 69 68 67
P34
P33
P35
P36
P16
P18
P17
P19
P37
P39
P38
P40
VS
AIN12 AIN5 AIN11 AIN4 AIN10 AGND CAPC2 CAPC1 BIAS AGND CML REFOUT AVDD CAPY2 CAPY1 AGND NC AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG AGND
ADV7400A
66 65 64
LQFP TOP VIEW (Not to Scale)
63 62 61 60 59 58 57 56 55 54 53 52 51
27
31
37
38
39
42
48
49
26
33
34
44
29
30
35
36
40
41
45
46
28
32
ELPF
XTAL1
DCLK_IN
DGND
DVDD
PVDD
PVDD
XTAL
AGND
Figure 2. LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 5, 11, 17, 40, 89 49, 50, 51, 60, 66, 70 6, 18 12, 39, 90 63 47, 48 54, 56, 58, 72, 74, 76, 53, 55, 57, 71, 73, 75 42, 41, 28, 27, 26, 25, 23, 22, 10, 9, 8, 7, 94, 93, 92, 91 33, 32, 31, 30, 29, 24, 14, 13 44, 43, 21, 20, 45, 34, 2, 1, 100, 97, 96, 95, 88, 87, 84, 83 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1 to AIN12 Type G G P P P P I Description Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels.
P2 to P9, P12 to P19 P22 to P29 P0, P1, P10, P11, P20 to P21, P31 to P40
O
Video Pixel Output Port.
I/O I
Video Pixel Input/Output Port. Video Pixel Input Port.
Rev. A | Page 8 of 16
AGND
LLC1
05000-002
NC = NO CONNECT
P25
P6
P26
P23
P22
P21
P3
43
P24
P20
P4
P1
P5
P2
P0
47
50
ADV7400A
Pin No. 3 Mnemonic INT Type O Description Interrupt Pin. This pin can be programmed active low or active high. When SDP/CP status bits change, this pin triggers an interrupt. The set of events which triggers an interrupt can be modified via I2C registers. Horizontal Synchronization/Composite Synchronization. HS is a horizontal synchronization output signal in SDP and CP modes. CS is a digital composite synchronization signal that can be selected while in CP mode. Vertical Synchronization. Vertical synchronization output signal in SDP and CP modes. Field Synchronization/Data Enable. Field synchronization output signal in all interlaced video modes. This pin also can be enabled as a data enable signal in CP mode to allow direct connection to a HDMI/DVI Tx IC. I2C Port Serial Data Input/Output Pin. SDA1 is the data line for the control port and SDA2 is the data line for the VBI readback port. I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the control port, and SCLK2 is the clock line for the VBI data readback port. This pin selects the I2C address for the ADV7400A control and VBI readback ports. When set to a Logic 0, ALSB sets the address for a write to control port of 0x40 and the readback address for the VBI port of 0x21. When set to a Logic 1, ALSB sets the address for a write to the control port of 0x42 and the readback address for the VBI port of 0x23. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7400A circuitry. Line-locked output clock for the pixel data output by the ADV7400A (the range is 13.5 MHz to 110 MHz for the ADV7400AKSTZ-110; 13.5 MHz to 80 MHz for the ADV7400AKSTZ-80). Input pin for 27 MHz crystal, or it can be overdriven by an external 3.3 V 27 MHz clock oscillator source to clock the ADV7400A. This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7400A. In crystal mode the crystal must be a fundamental crystal. The recommend external loop filter must be connected to this ELPF pin. SFL (Subcarrier Frequency Lock). This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal available only in CP mode. Internal Voltage Reference Output. Common-Mode Level Pin for the Internal ADCs. ADC Capacitor Network. ADC Capacitor Network. External Bias Setting Pin. Connect the recommended resistor between this pin and ground. Can be configured in CP mode to be either a digital HS input signal or a digital CS input signal, which are used to extract timing in 5-wire or 4-wire RGB mode. VS Input Signal. Used in CP mode for 5-wire timing mode. Data Enable Input Signal. Used in 24-bit digital input port mode, for example, 24-bit RGB data from a DVI Rx IC. No Connect Pin. This pin can be tied to AGND or AVDD. Clock Input Signal. Used in 24-bit digital input mode and also in digital CVBS input mode. Sync On Green Input Pin. Used in embedded sync mode. Sync On Luma Input Pin. Used in embedded sync mode.
4
HS/CS
O
99 98
VS FIELD/DE
O O
81, 19 82, 16 80
SDA1, SDA2 SCLK1, SCLK2 ALSB
I/O I I
78 36
RESET LLC1
I O
38 37
XTAL XTAL1
I O
46 15
ELPF SFL/SYNC_OUT
O O
64 65 61, 62 68, 69 67 86 85 79 59 35 52 77
REFOUT CML CAPY1 to CAPY2 CAPC1 to CAPC2 BIAS HS_IN/CS_IN VS_IN DE_IN NC DCLK_IN SOG SOY
O O I I O I I I NC I I I
Rev. A | Page 9 of 16
ADV7400A DETAILED FUNCTIONALITY
ANALOG FRONT END
* * * Three high quality 10-bit ADCs enable true 8-bit video decoder 12 analog input channel mux enables multisource connection without the requirement of an external mux Three current and voltage clamp control loops ensure any dc offsets are removed from the video signal * * * Luminance digital noise reduction (DNR) Color controls include hue, brightness, saturation, contrast, and Cr and Cb offset controls Certified Macrovision(R) copy protection detection on composite and S-video for all worldwide formats (PAL/NTSC/SECAM) 4x oversampling (54 MHz) for CVBS and S-video modes Line-locked clock output (LLC) Letterbox detection supported Free-run output mode provides stable timing when no video input is present Vertical blanking interval data processor Closed captioning (CC) and extended data service (EDS) Wide screen signaling (WSS) Copy generation management system (CGMS) EDTV GemstarTM 1x/2x electronic program guide-compatible Clocked from a single 27 MHz crystal Subcarrier frequency lock (SFL) output for downstream video encoder Differential gain typically 0.5% Differential phase typically 0.5
* * * * * * * * * * * * * *
SDP PIXEL DATA OUTPUT MODES
* * * 8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD 16-bit YCrCb with embedded time codes and/or HS, VS, and FIELD 24-bit YCrCb with embedded time codes and/or HS, VS, and FIELD
CP PIXEL DATA OUTPUT MODES
* * * * Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all standards Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all standards
COMPOSITE AND S-VIDEO PROCESSING
* Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N, Nc 60) and SECAM B/D/G/K/L standards in the form of CVBS and S-video Super adaptive 2D 5-line comb filters for NTSC and PAL give superior chrominance and luminance separation for composite video Full automatic detection and autoswitching of all worldwide standards (PAL/NTSC/SECAM) Automatic gain control with white peak mode ensures the video is always processed without loss of the video processing range Adaptive digital line length tracking (ADLLT) Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners IF filter block compensates for high frequency luma attenuation due to tuner SAW filter Chroma transient improvement (CTI)
Rev. A | Page 10 of 16
*
COMPONENT VIDEO PROCESSING
* * Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, and many other HDTV formats Automatic adjustments include gain (contrast) and offset (brightness); manual adjustment controls are also supported Support for analog component YPrPb/RGB video formats with embedded sync or with separate HS, VS, or CS Any-to-any 3 x 3 color space conversion matrix supports YCrCb-to-RGB and RGB-to-YCrCb Standard identification (STDI) enables system level component format detection Certified Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p)
* *
* * * *
* * * *
ADV7400A
* * Free-run output mode provides stable timing when no video input is present Arbitrary pixel sampling support for nonstandard video sources
DIGITAL VIDEO INPUT PORT
* * * Support for raw 10-bit CVBS data from digital tuner Support for 24-bit RGB input data from DVI Rx chip, output converted to YCrCb 4:2:2 Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, VGA to SXGA @ 60 Hz input data from HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
RGB GRAPHICS PROCESSING
* 110 MSPS conversion rate supports RGB input resolutions up to 1280 x 1024 @ 60 Hz (SXGA); (80 MSPS conversion rate for ADV7400AKSTZ-80) Automatic or manual clamp and gain controls for graphics modes Contrast and brightness controls Sampling PLL clock with 500 ps p-p jitter at 110 MSPS 32-phase DLL allows optimum pixel clock sampling Automatic detection of sync source and polarity by SSPD block Standard identification is enabled by STDI block RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for video centric backend IC interfacing Data enable (DE) output signal supplied for direct connection to HDMI/DVI Tx IC Arbitrary pixel sampling support for nonstandard video sources
* * * * * * *
GENERAL FEATURES
* * * * HS, VS, and FIELD output signals with programmable position, polarity, and width Programmable interrupt request output pin, INT, signals SDP/CP status changes Supports two I2C host port interfaces (control and VBI) Low power consumption: 1.8 V digital core, 3.3 V analog and digital I/O, low power power-down mode, and green PC mode Industrial temperature range (-40C to +85C) 110 MHz and 80 MHz speed grades (ADV7400AKSTZ110 and ADV7400AKSTZ-80) 100-pin 14 mm x 14 mm Pb-free LQFP package
* * *
* *
Rev. A | Page 11 of 16
ADV7400A DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7400A analog front end includes three 10-bit ADCs, which digitize the analog video signal before applying it to the SDP or CP (see Table 8 for sampling rates). The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 12-channel input mux, which enables multiple video signals to be applied to the ADV7400A. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping either in the CP or SDP. The ADCs are configured to run in 4x oversampling mode when decoding composite and S-video inputs; 2x oversampling is performed for component 525i, 625i, 525p, and 625p sources. All other video standards are 1x oversampled. Oversampling the video signals reduces the cost and complexity of external anti-aliasing filters. This has the benefit of an increased signalto-noise ratio (SNR). Table 8. Maximum ADC Sampling Rates
Model ADV7400AKSTZ-80 ADV7400AKSTZ-110 Max ADC Sampling Rate 80 MHz 110 MHz
The ADV7400A implements a patented adaptive-digital-linelength-tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7400A to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The SDP contains a chroma transient improvement (CTI) processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1x/2x, and extended data service (XDS). The ADV7400A SDP section has a Macrovision 7.1 detection circuit, which allows it to detect Types I, II, and III protection levels. The decoder is fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, VGA up to SXGA @ 60 Hz, and many other standards not listed here. The CP section of the ADV7400A also contains an automatic gain control (AGC) block. In cases where no embedded sync is present, the video gain can be set manually. The AGC block is followed by a digital clamp circuit that ensures the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); manual adjustment controls are also supported. A fully programmable any-to-any 3 x 3 color space conversion matrix is placed between the analog front end and the CP section. This enables YPrPb to RGB and RGB to YCrCb conversions. Many other standards of color space may be implemented using the color space converter. The output section of the CP is highly flexible. It can be configured in single data rate mode (SDR) with one data packet per clock cycle or in a double data rate (DDR) mode where data is presented on the rising and falling edge of the clock. In SDR mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these modes HS, VS, and FIELD/DE (where applicable) timing reference signals are provided. In DDR mode, the ADV7400A can be configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb pixel output interface with corresponding timing signals.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of baseband video signals in composite and S-video formats. The video standards supported by the SDP include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7400A can automatically detect the video standard and process it accordingly. The SDP has a 5-line super adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue.
Rev. A | Page 12 of 16
ADV7400A
The ADV7400A is capable of supporting an external DVI/ HDMI receiver. The digital interface expects 24-bit 4:4:4 or 16-bit 4:2:2 bit data (either graphics RGB or component video YCrCb), accompanied by HS, VS, DE, and a fully synchro-nous clock signal. The data is processed in the CP and output as 16bit 4:2:2 YCrCb data. The CP section contains circuitry to enable the detection of Macrovision encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI extraction of CGMS data is performed by the CP section of the ADV7400A for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. For more detailed product information about the ADV7400A, contact your local ADI sales office or email video.products@analog.com.
Rev. A | Page 13 of 16
ADV7400A TIMING DIAGRAMS
t3
SDA1/SDA2
t5
t3
t6
SCLK1/SCLK2
t1
05000-003
t2
t7
t4
t8
Figure 3. I2C Timing
t9
LLC1
t10
t11
P2-P9, P12-P19, P22-P29, VS, HS, FIELD/DE, SFL/SYNC_OUT
t12
05000-004
Figure 4. Pixel Port and Control Output SDR Timing (SD Core)
t9
LLC1
t10
t13 t14
P2-P9, P12-P19, P22-P29
05000-005
Figure 5. Pixel Port SDR Timing (CP Core)
LLC1
t16 t15
P6-P9, P12-P19
t18
05000-006
t17
Figure 6. Pixel Port DDR Timing (CP Core)
Rev. A | Page 14 of 16
ADV7400A
t9
LLC1
t10
t13 t14
VS, HS, FIELD/DE
05000-007
Figure 7. Control Output SDR/DDR Timing (CP Core)
DCLK_IN
t9
CONTROL INPUTS HS_IN VS_IN DE_IN
t10
t20
t19
Figure 8. Digital Input Port and Control Input Timing
Rev. A | Page 15 of 16
05000-008
P0-P1, P10-P11, P20-P21, P22-P29, P31-P32, P33-P40
ADV7400A OUTLINE DIMENSIONS
1.60 MAX 0.75 0.60 0.45
100 1 PIN 1
16.00 BSC SQ
76 75
14.00 BSC SQ TOP VIEW
(PINS DOWN)
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
25 26
51 50
VIEW A
0.50 BSC LEAD PITCH
VIEW A
ROTATED 90 CCW
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 9. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters
ORDERING GUIDE
Model ADV7400AKSTZ-1101 ADV7400AKSTZ-801 ADV7400ABSTZ-1101 EVAL-ADV7400AEBM
1
Temperature Range -25C to +70C -25C to +70C -40C to + 85C
Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP Evaluation Board
Package Option ST-100 ST-100 ST-100
Z = Pb-free part. The ADV7400A is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255C (5C). In addition, it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220C to 235C.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05000-0-3/05(A)
Rev. A | Page 16 of 16

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